1. Field of the Invention
This invention relates to the field of electronics, and in particular to a device that facilitates the interconnection of devices using an I2C interface.
2. Description of Related Art
The Inter Integrated Circuit (I2C) bus developed by Philips Corporation allows integrated circuits to communicate directly with each other via a simple bi-directional 2-wire (plus ground) bus. A device connects to each of the two wires on the bus, one (SData) for the communication of data, and the other (SClk) for the control and synchronization of the communication of data between the devices. Each device is connected in parallel to each of the other devices, and each of the bus lines, SData and SClk, function as a wired-AND of all the lines on the bus. The output of each device is configured as an open-collector/open-drain device, and one or more pull-up resistors maintain a xe2x80x98softxe2x80x99 logic high value on the bus while the bus is in the quiescent state. When a device desires access to the bus, the device pulls the bus to a logic low value, via the open-collector/open-drain device that is placed in a conductive state to ground potential.
To facilitate a high speed data transfer, the I2C specification limits the maximum capacitive loading on the bus, thereby limiting the maximum length of the bus. The specified maximum capacitive loading is 400 pf, which limits the bus length to a few meters. The 82B715 integrated circuit from Philips Semiconductors is an I2C bus extender that allows for routing of the bus beyond the specified maximum length. The 82B715 offers a current gain of ten from the input to the output, thereby providing a capacitive reduction of ten to the bus on the input side of the bus extender. By placing a bus extender at each end of a long length of wire, only one tenth of the capacitance of the wire appears as a load to the I2C bus or device at each end of the long length of wire. The current buffering also preserves the bi-directional, open-collector/open-drain characteristics of the I2C bus.
A hub is distinguished from an extender in that a hub is conventionally defined as a device that distributes a signal to multiple devices. For example, on a printed circuit board, a hub may be centrally placed among a variety of devices that communicate via the bus. From this central location, the bus is distributed to each device, preferably via a driver on each port of the bus that drives a corresponding segment of the bus. In this manner, the length of each segment of the bus, from the hub to the devices, is reduced, relative to one continuous length of wire extending to all devices, and the bus loading is distributed among the hub drivers.
In a bi-directional configuration, wherein the same wire is used to both transmit and receive, a hub appears as a collection of input ports that each fan out to a driver at every other port. Because the output of the driver at a port shares the same node as the input from the devices on that port""s segment of the bus, and the input fans out to every other driver, a bi-directional hub must be configured to distinguish an externally generated event on the bus segments from an internally generated event, to preclude a latch-up. Such a latch-up is caused when an input event that is propagated from one port is interpreted as an input event from another port, and re-propagated to the originating port from the other port. When the originator of the event ceases the event, this cessation must be propagated to all the ports.
Conventional bi-directional hubs typically include control logic that determines which port is receiving a driving signal, and thereafter blocks any input from any other port from being propagated to any port. That is, the conventional hub selectively enables only one port as a receiving port, and forces all other ports to a transmit state, wherein these other ports transmit the data received at the receiving port to their corresponding bus segments. Because only one port is enabled for receiving and propagating a signal at any one time, the possibility of a latch-up is avoided. Note, however, that this selective enabling of one port at a time presupposes that only one port may be active at any point in time, or, if two ports are active, the first port to be active prevails.
Preferably, a hub is xe2x80x9ctransparentxe2x80x9d to devices on the bus. That is, although a hub allows for improved bus performance, its presence on the bus should be undetectable. If the bus without the hub is a wired-AND bus, for example, when any device pulls the bus low, the entire length of the bus is brought to the low state. If multiple devices pull the bus low, the bus will remain low until the last device ceases to assert the low voltage. A conventional hub that only reacts to one port at a time will often introduce transition behavior as it disables the current receiving port, and then enables another port as the receiving port. Because only one port at a time is enabled as a receiving port, the hub is unaware that another segment of the bus is also being driven low until it attempts to bring the bus to a high level. The segment being driven low will remain low, but other segments will be allowed to rise to the high level until the port that is being driven low is enabled as the sole receiving port. Some specifications, and in particular the I2C specification, rely upon a consistent performance in the presence of a simultaneous assertion of the active state by more than one device. In the I2C specification, for example, the synchronization of the clock signal among multiple devices is determined by the time that a first device pulls the bus low, and the time that a last device ceases pulling the bus low.
It is an object of this invention to provide a multiport device that facilitates a multiple fanout of an open-collector/open-drain bus while also providing for a high-speed data transfer. It is a further object of this invention to provide a multiport device that maintains the bus control protocol of an I2C bus. It is a further object of this invention to provide a multiport device that minimizes propagation delays.
These objects and others are achieved by providing a multiport device that is configured to recognize each active segment on the bus. The propagation of signals from each port to each other port is controlled by state of each segment. Optimal signal propagation is achieved by invoking the control of the propagation of signals only after a first active-transition on the bus. Initial transitions are propagated unconditionally, to minimize propagation delay, and subsequent signal propagations are conditionally controlled, to avoid latch-up. A latch is associated with each port. The latch is set each time the port is actively driven by a device on that port. The latch is reset when all the devices are in the quiescent state, or when another port remains active after the currently active port becomes inactive. The state of each port""s latch controls the propagation of internally generated signals to the port. If the latch is set, internally generated signals are not propagated to the port, thereby preventing latch-up. If the latch is not set, both internally generated signals and externally generated signals are propagated to the port, thereby minimizing propagation delays.